1. Field of the Invention
This invention relates to a semiconductor circuit and especially to a sense amplifier circuit provided for a semiconductor memory device having MOS (Metal Oxide Semiconductor) type transistor memory cells.
2. Description of the Prior Art
In the conventional semiconductor memory device, several types of sense amplifier circuits are employed. To obtain high speed and low power characteristics, CMOS (Complementary Metal Oxide Semiconductor) circuits are often used for the sense amplifier. A typical sense amplifier is disclosed in "ISSCC 1983 Digest of technical paper". This circuit consists of two single-ended active load differential amplifiers. Each amplifier includes two P-channel load transistors connected to a constant voltage supply and two N-channel sensing transistors connected between the load transistors and a ground voltage, respectively. The gate electrodes of the sensing transistors are connected to two bit lines, respectively. The bit lines are connected to a memory cell array. According to the information stored in the memory cells, the voltage balance of the two bit lines are changed. The sense amplifier detects and amplifies the change of the voltage balance.
In order to achieve a high switching speed, consideration must be given to the layout of the transistors. Generally the time t in which the change .DELTA.V of the voltage balance of the two bit lines appears after the memory is accessed, has the following relation: EQU t.congruent.C.sub.BL .multidot..DELTA.V/I
Here, C.sub.BL is the capacitance associated with the bit line and I is the current flowing through the bit line. Accordingly, the following approaches may be utilized to achieve the high speed response:
(1) Reducing the bit line capacitance C.sub.BL, PA0 (2) Reducing the voltage change .DELTA.V, PA0 (3) Making the bit line current I larger.
It is, however, difficult to realize the first and third approaches. Namely, first of all, in order to achieve a higher cell packing density, which is another important requirement for a memory device, the channel width of the transistors of which the memory cells are constructed must be smaller. Therefore the bit line current may also be smaller. Next, as the number of cells connected to a bit line increases, the number of transfer gate transistors connected between the bit line and the memory cells, also increases. This increases the capacitance attached to the bit line.
Accordingly it is necessary to utilize the second approach to achieve a high speed response. However, it is also difficult to establish .DELTA.V at a smaller level. It .DELTA.V becomes smaller, the conductance of the sensing transistors must be larger and the channel width of the transistor must be larger. This is contrary to high packing density. Further, in case that .DELTA.V is low, the distribution of Vth, the threshold voltage of the MOS sensing transistor, produced in the manufacturing process seriously affects the characteristics of the device.
There is another problem in the conventional device. Namely, the change of bit line voltage .DELTA.V occurs near the supply voltage V.sub.DD, but the most sensitive voltage range of the sense amplifier is near the threshold voltage Vth of the MOS sensing transistor. Generally Vth is so far from V.sub.DD that the sensing ability is not effectively used.
As mentioned above, it is very difficult to achieve a higher speed characteristic and a higher packing density at the same time by using a sense amplifier formed of MOS transistors. In order to overcome this problem, especially to achieve the higher speed characteristic, a bipolar transistor may be applied to the sense amplifier.
Referring to FIG. 1, we will explain a sense amplifier circuit including emitter coupled bipolar transistors used for a conventional ECL circuit. In this circuit, input signals V.sub.H, V.sub.L are applied to the base electrodes of bipolar transistors 7, 8. The collector electrodes of the transistors 7, 8 are connected to a constant voltage supply V.sub.DD through resistors 9, 10 respectively and also connected to respective output terminals of this circuit. The emitter electrodes of transistors 7, 8 are connected to a constant current source formed of a bipolar transistor 11, resistor 12 and a control voltage supply V.sub.CCB. In this circuit, the ratio I.sub.H to I.sub.L, wherein I.sub.H is the current in the higher bit line and I.sub.L in the lower one, is as follows: ##EQU1## Here, q is the elementary electric charge, K is the Boltzman constant and T is the temperature. In the case KT/q=25 mV, .DELTA.V=0.4 V, I.sub.H /I.sub.L becomes 10.sup.7. Further, the difference of the lower output voltage V.sub.OL from the higher output voltage V.sub.OH is as follows: EQU V.sub.OH -V.sub.OL =R(I.sub.H -I.sub.L).congruent.RI.sub.H .congruent.RI
Namely, the bipolar transistor has a very high sensitivity because the collector current is very sensitive to the change of the bit line voltage. Further, the bipolar transistor also has the advantage of small Vth distribution produced in the manufacturing process.
However, the bipolar transistor in this circuit also has the following disadvantage to be overcome. That is, it needs elements other than the MOS circuit. Particularly, it needs an extra constant voltage source V.sub.CCB for controlling the constant current source. Further, the resistors 9,10 occupy a very large portion on the chip because the resistance must be large so as to obtain an efficient output voltage.